In a semiconductor memory device, mainly, an electric charge is accumulated in a memory cell capacitor formed within a semiconductor device, and the data is stored depending on presence or absence of the electric charge (generally called dynamic memory or DRAM). In this memory cell capacitor, hitherto, a silicon oxide film was used as a capacity insulation film. Recently, using a ferroelectric material as a capacity insulation film of a memory cell capacitor, a semiconductor memory device for realizing nonvolatility of stored data is proposed.
A semiconductor memory device using a ferroelectric film as a capacity insulation film of a memory cell capacitor is described below.
FIG. 9 is a circuit block diagram of a conventional semiconductor memory device.
In FIG. 9, reference numerals 30a to 30d are memory cells, and 31a to 31d are memory cell transistors. Reference numerals 32, 34 are word lines, and 33a to 33d are memory cell capacitors. Reference numerals 35 to 38 are bit lines, and 39, 40 are cell plate lines. Reference numerals 41, 42 are sense amplifiers, 43 to 46 are bit line precharging transistors, BLP is a bit line precharge control signal, and SAE is a sense amplifier control signal.
As shown in FIG. 9, in a circuit configuration of a conventional semiconductor memory device, the bit line 35 (BL0) and bit line 36 (/BL0) are connected to the sense amplifier 41. Two memory cells 30a, 30b are connected to these bit lines 35, 36.
In the memory cell 30a, two memory cell capacitors 33a and two MOS transistors are provided. These two memory cell capacitors 33a have two electrodes individually. One electrode of the two electrodes of one memory cell capacitor 33a (located at the left side in the drawing) is connected to the bit line 35 through the MOS transistor 31a (located at the left side in the drawing), and the other electrode is connected to the cell plate line 39. The other one of the two electrodes of the memory cell capacitor 33a (located at the right side in the drawing) is connected to the bit line 36 through the MOS transistor 31a (located at the right side in the drawing), and the other electrode is connected to the cell plate line 39. Each gate of the two MOS transistors 31a is connected individually to the word line 32 (word line 0).
The memory cells 30b to 30d are composed same as the memory cell 30a.
The bit lines 35, 36 are connected to the grounding potential (VSS) through the MOS transistors 43, 44 controlled by the bit line precharge control signal BLP.
In the conventional semiconductor memory device shown in FIG. 9, one memory cell 30a is composed of two memory cell capacitors 33a and two MOS transistors 31a. When writing data, one of the two memory cell capacitors 33a is written in logic voltage "H", and the other in logic voltage "L", and when reading out the data, the potential difference being read out from the two memory cell capacitors 33a is amplified by the sense amplifier 41 and the data is read out.
The operation of the ferroelectric memory using a ferroelectric material as a capacity insulating film is described below while referring to FIG. 10 and FIG. 11. FIG. 10 is a diagram for explaining reading of data in the memory cell in the conventional semiconductor memory device, and a hysteresis curve of ferroelectric is shown.
In the capacitor using ferroelectric material as a capacity insulating film, a residual electric field is left over as indicated at point B and point E even if the voltage is 0 as shown in FIG. 10.
Thus, by utilizing the residual electric field left over in the ferroelectric capacitor even after turning off the power source as nonvolatile data, a nonvolatile semiconductor memory device is realized.
That is, when the data of the memory cell 30a is "1," one memory cell capacitor 33a (called first memory cell capacitor) out of two memory cell capacitors 33a is in the state of point B, and the other memory cell capacitor 33a (called second memory cell capacitor) is in the state of point E.
When the data of the memory cell 30a is "0," contrary to the case above, the first memory cell capacitor is in the state of point E, and the second memory cell capacitor, in the state of point B.
FIG. 11 is an operation timing diagram of a conventional semiconductor memory device.
In the initial state, the bit lines 35, 36, word lines 32, 34, cell plate line 39, and sense amplifier control signal SAE are all at logic voltage "L," and the bit line precharge control signal BLP is at logic voltage "H." In this state, first, the bit line precharge control signal BLP is at logic voltage "L," and the bit lines 35, 36 are in floating state. Next, the word line 32 and cell plate line 39 are set at logic voltage "H," and the two MOS transistors 31a are turned on. At this time, an electric field is applied in each of the two memory cell capacitors 33a, and data is being read out in the bit lines 35, 36 from the memory cell 30a.
The voltage difference being read out in the bit lines 35, 36 at this time is described while referring to FIG. 10.
In FIG. 10, reference numerals L1, L2 are lines having an inclination determined by the parasitic capacity value of the bit lines 35, 36.
That is, when the data being read out is "1," data is read out in the bit line 35 from one memory cell capacitor 33a (the first memory cell capacitor), thereby changing from the state of point B to the state of point O21.
The point O21 is the intersection of a hysteresis curve moving from point B toward point D when a voltage is applied to the memory cell capacitor 33a, and a line L1 passing through a point M21 moving on the axis of abscissas from point B by the portion of the voltage caused when the logic voltage of the word line 32 and cell plate line 39 is "H."
Similarly, in the bit line 36, data is read out from the other memory cell capacitor 33a (the second memory cell capacitor), changing from the state of point E to the state of point P21. The point P21 is the intersection of a hysteresis curve moving from point E toward point D when a voltage is applied to the memory cell capacitor 33a, and a line L2 passing through a point N21 moving on the axis of abscissas from point E by the portion of the voltage caused when the logic voltage of the word line 32 and cell plate line 39 is "H". Herein, the voltage difference being read out at the bit line 35 and bit line 36 is a difference Vr21 of the voltages at point O21 and point P21. It is the same when the data being read out is "0", and only the state of the bit line 35 and bit line 36 is inverted, and the potential difference being read out is Vr21. Incidentally, the reversed state of bit line 35 and bit line 36 is also shown in FIG. 11.
Next, setting the sense amplifier control signal SAE to logic voltage "H", the data being read out in the bit line 35 and bit line 36 is amplified by the sense amplifier 41, and the data is read out. When amplified by this sense amplifier 41, the state of the bit line 35 is changed from point O21 to point Q21, and the state of the bit line 36 is changed from point P21 to point D.
Then, as the data rewriting state, the cell plate line 39 is set at logic voltage "L". At this time, in FIG. 10, the state of the bit line 35 is changed from point Q21 to point A, and the state of the bit line 36, from point D to point E. Consequently, the sense amplifier control signal SAE is set to logic voltage "L."
Afterwards, setting the bit line precharge control signal BLP to logic voltage "H", setting the bit lines 35, 36 to logic voltage "L", and finally setting the word line to logic voltage "L", there is no voltage difference between both terminals of the ferroelectric capacitor of the memory cell, and the state of point B and point E in FIG. 10 is established, thereby returning to the initial state. As a result, rewriting operation is over.
However, in the semiconductor memory device of such conventional constitution and operation, in spite of rewriting operation, the residual charge of the ferroelectric disappears and the "L" data of the memory cell may be lost. The cause of such data loss was not disclosed yet.